AS4C128M8D3LB-12BCN Information

DDR3 Synchronous DRAM

Alliance Memory DDR3 Synchronous DRAM (SDRAM) achieve high speed double-data-rate transfer rates of up to 1600 Mb/sec/pin for general applications. The chip is designed to comply with all key DDR3 DRAM key features and all of the control and address inputs are synchronized with a pair of externally supplied differential clocks. Inputs are latched at the cross point of differential clocks (CK rising and CK# falling). All I/Os are synchronized with differential DQS pair in a source synchronous fashion. These devices operate with a single 1.5V ± 0.075V power supply and are available in BGA packages.

DDR3L SDRAM

Alliance Memory DDR3L SDRAM uses a double data rate architecture to achieve high-speed operation. The double data rate architecture is an 8n-prefetch architecture with an interface designed to transfer two data words per clock cycle at the I/O pins. A single read or write operation for the DDR3 SDRAM effectively consists of a single 8n-bit-wide, four-clock-cycle data transfer at the internal DRAM core and eight corresponding  n-bit-wide, one-half-clock-cycle data transfers at the I/O pins.

Specifications

AS4C128M8D3LB-12BCN Price & Stock

Alliance Memory AS4C128M8D3LB-12BCN pricing and available inventory.

AD5242BRUZ1M distributor

Alternate Names

Alliance Memory has several brands around the world that may have alternate names for AS4C128M8D3LB-12BCN due to regional differences or acquisition. AS4C128M8D3LB-12BCN may also be known as the following names: